The present invention generally relates to planarization methods, and more particularly to a method of planarizing a metal layer by a pulse energy beam such as a pulse laser beam. The method of the present invention is especially suited for planarizing a metal interconnection layer.
When forming a metal interconnection layer during a process of producing an integrated circuit, a conductor layer 4 shown in FIG. 1 is formed on an insulator layer 2 which is provided on a semiconductor layer 1 by a vapor deposition, sputtering or the like. However, as a via hole 5 such as a contact hole and a through hole in the insulator layer 2 becomes smaller, the conductor layer 4 does not sufficiently fill the via hole 5 and the step coverage becomes poor. This poor step coverage is caused by the fact that it becomes difficult for the conductor layer 4 to adhere on the sidewall of the via hole 5 due to the shadowing effect.
FIG. 2 is a cross sectional view for explaining a proposed method of eliminating the poor step coverage described above. According to this proposed method, a laser beam is irradiated on the conductor layer 4 to melt and planarize the conductor layer 4.
On the other hand, FIGS. 3 and 4 are cross sectional views for explaining a proposed method of forming a plug to eliminate the problem of poor step coverage. According to this proposed method, the conductor layer 4 is formed in a vicinity of the via hole 5 as shown in FIG. 3, and a laser beam is irradiated on the conductor layer 4 to form a plug 6 within the via hole 5 by the melted conductor as shown in FIG. 4.
However, an alignment mark 3 is usually formed on the conductor layer 4 as shown in FIG. 5. This alignment mark 3 is used for aligning a mask relative to the conductor layer 4. When the laser beam irradiates the conductor layer 4, the laser beam irradiates the entire surface of the conductor layer 4 because the laser beam irradiation is made with respect to the conductor layer 4 on a wafer, for example, so as to improve the throughput of the device. For this reason, the alignment mark 3 is also planarized by the laser beam irradiation as shown in FIG. 6, and there is a problem in that the alignment mark 3 disappears when the planarization using the laser beam is carried out. On the other hand, if the laser beam irradiation is made to avoid the alignment mark 3, it is necessary to irradiate the laser beam on the conductor layer 4 on the wafer in parts, and the throughput of the device becomes poor because of the need to make several laser beam irradiations with respect to the conductor layer 4 on the wafer.